1. Field of the Invention
The present invention relates generally to systems having multiple integrated circuits, and more particularly to maintaining synchronization in such systems by adjusting the delay of the clock signal distributed in each integrated circuit.
2. Description of the Related Art
The performance of electronic systems having multiple integrated circuits (xe2x80x9cICsxe2x80x9d) is largely dependent on the ability of the system to transmit digital data between ICs quickly and efficiently. To maximize speed and efficiency in these systems, each IC in the system can be synchronized to a common clock signal, or reference clock. When each IC in the system is synchronized to the same reference clock, the read and write functions of each IC can be coordinated by a common controller, that coordinates the operation of the ICs based on the rising or falling edge of the reference clock signal.
Because the synchronization of the system is dependent on a reference clock signal, it is essential that the reference clock signal is accurately distributed to each IC in the system. Typically, each IC in the system has one or more clock terminals which receive the reference clock signal. The reference clock signal is then distributed to each of the clocked circuit elements within the IC.
Due to the physical properties of the ICs, the reference clock signal is delayed as it is distributed to each circuit element in each IC. In other words, a rising edge of the reference clock signal arrives at the clocked circuitry of an IC some finite time later than it was received at the clock terminals of that IC. This delay is often referred to as inherent delay because it is due to the physical properties and design of the IC.
Inherent delay in the distribution of the reference clock signal in each IC would not be a problem if each IC in the system had the identical inherent delay. Due to differences in the physical properties of individual ICs, however, inherent delays vary from IC to IC. Even two ICs of the same make and model can have different inherent delays because of, for example, variables in the manufacturing process. It is difficult to economically and practically design and manufacture ICs with identical inherent delays. Therefore, some method and apparatus is needed to compensate for the varying inherent delays in the ICs to maintain synchronization in the system.
One existing device for compensating for clock delay in multiple IC systems is a delay-locked loop (xe2x80x9cDLLxe2x80x9d). A DLL is a device resident in each IC that continuously adjusts the clock delay in that IC. A DLL typically consists of a variable delay line and control logic. The variable delay line produces a delayed version of the reference clock. The delayed version of the reference clock is distributed to all clocked elements in the IC and to a clock feedback terminal. The control logic samples the reference clock as well as the clock signal at the feedback terminal in order to adjust the delay line. The variable delay line of the DLL introduces delay into the reference clock signal until the rising edges of the reference clock are aligned to the rising edges of the clock signal sampled at the feedback terminal. Once aligned, there is zero phase delay between the reference clock signal and the clock signal sampled at the feedback terminal.
Another existing device for compensating for clock delay in multiple IC systems is a phase-locked loop (xe2x80x9cPLLxe2x80x9d). A PLL, like a DLL, is a device resident in each IC that continuously adjusts the clock delay in that IC. A PLL, like a DLL, compares the reference clock signal to the clock signal sampled at the feedback terminal. The PLL uses a voltage controlled oscillator to generate a clock signal that approximates the reference clock signal, but adjusts for the clock delay. The control logic adjusts the oscillator clock until the rising edges of the reference clock align with the rising edges of the clock signal sampled at the feedback terminal. Once aligned, there is zero phase delay between the reference clock signal and the clock signal sampled at the feedback terminal.
One limitation of existing methods and systems for adjusting clock delay is that they become misaligned if the frequency of the reference clock changes. PLLs and DLLs, for example, continuously adjust clock delay to maintain zero phase delay between the reference clock signal and the feedback clock signal. When the reference clock frequency changes, a phase delay results, and PLLs and DLLs must realign the reference and feedback clock signals. Realignment, however, is not instantaneous. It may take several clock cycles to realign the clock rising edges. During the finite period of time DLLs and PLLs take to adjust the clock delays in the ICs, the ICs in the system are not synchronized and cannot exchange data.
In many applications, however, it is necessary to instantaneously change the frequency of the reference clock. Therefore, the effectiveness of existing appartuses and methods in maintaining clock alignment is limited because they become temporarily misaligned during reference clock frequency changes.
Therefore, it would be desirable to provide a method and apparatus for adjusting the clock delay in systems with multiple ICs. It would also be desirable to provide a method and apparatus for adjusting the clock delay in systems with multiple ICs wherein the system will not become misaligned when the frequency of the reference clock changes.
A system in accordance with the present invention is able to adjust the clock delay in a system with multiple integrated circuits such that all the integrated circuits can be synchronized. The synchronization will not become misaligned when the frequency of the reference clock changes. The present invention also provides a method for accomplishing these objectives, as well as a method for identifying which of a group of integrated circuits has the longest inherent delay.
The apparatus for adjusting the clock delay in a system having multiple integrated circuits can include a clock generator for generating a reference (or a first) clock signal. A controller is used to control the frequency of the first clock signal. The apparatus also includes a means for creating a second clock signal derived from the first clock signal. For example, the second clock signal can simply be a delay of the first clock signal. The apparatus also includes a means for sampling the first clock signal at a time determined by the second clock signal. The sampling means can be, for example, a flip-flop or a latch. The flip-flop can have a data input terminal, a data output terminal and a clock input terminal. Finally, the apparatus includes a means for comparing the sampled first clock signal to a predetermined value. For example, if the apparatus uses a flip-flop clocked on the rising edge of a timing signal, the controller can determine whether the output of the flip-flop (which can be the first clock signal) is equal to a logic 0. In this way, the apparatus determines whether the delay in the second clock signal is long enough that the first clock signal has changed into the next logic state. This apparatus can be used to identify which integrated circuit has the longest inherent delay because the integrated circuit with the longest inherent delay will first cause this output.
A programmable clock generator can be used to generate the first clock signal. Each integrated circuit can include a programmable delay which can be programmed by the controller. Each integrated circuit can include a clock-fanout tree connected to the programmable delay. The clock-fanout tree can have at least one leaf terminal connected to the clock input terminal of the flip-flop.
If desired in a given application, the present invention also can be used to synchronize a plurality of integrated circuits by increasing the delay in the xe2x80x9cfasterxe2x80x9d integrated circuits so that all the integrated circuits have the same delay as the inherent delay in the integrated circuit having the longest inherent delay. In such case, the programmable delays are programmed to increase the delay in each integrated circuit to synchronize all the integrated circuits.
A method for determining which of a plurality of integrated circuits has the longest inherent delay can begin by setting the delay settings in the programmable delays of the integrated circuits to an initial delay. The initial delay can be zero. A first clock signal is generated and routed to the integrated circuits. In each integrated circuit, a respective second clock signal is derived from the first clock signal. For example, the second clock signal can simply be a delay of the first clock signal. On each integrated circuit, the respective second clock signal is distributed to clocked elements on the integrated circuit. The first clock signal is set to an initial frequency such that the period of the first clock signal is greater than twice the maximum inherent delay of the integrated circuits. In each integrated circuit, the first clock signal is sampled at a time determined by the second clock signal. For example, the second clock signal can be used to clock a flip-flop which accepts at the data input the first clock signal. The flip-flop thus will output the current value of the first clock signal. The frequency of the first clock signal can be incrementally increased until such time that the output from, e.g., the flip-flop has a predetermined value. The first integrated circuit to reach that state has the longest inherent delay.
If desired, the remaining integrated circuits can then be programmed to be synchronized with the integrated circuit having the longest inherent delay. The frequency of the first clock signal is held constant while each integrated circuit is adjusted as appropriate. In particular, the programmable delay in the integrated circuit is incrementally increased until such time that the output first clock signal has the desired predetermined value. This is done in all the integrated circuits so that they all are synchronized to that integrated circuit having the longest inherent delay. Once synchronized in this manner, a change in the frequency of the first clock signal will not disturb the synchronization thereby providing benefits over prior art systems and methods.